Reachability analysis using partitioned-ROBDDs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Design Constraints in Symbolic Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Constraint synthesis for environment modeling in functional verification
Proceedings of the 40th annual Design Automation Conference
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
The e Language: A Fresh Separation of Concerns
TOOLS '01 Proceedings of the Technology of Object-Oriented Languages and Systems
Optimal constraint-preserving netlist simplification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Efficient symbolic simulation via dynamic scheduling, don't caring, and case splitting
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Exploiting constraints in transformation-based verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Sequential equivalence checking based on structural similarities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Benchmarking a model checker for algorithmic improvements and tuning for performance
Formal Methods in System Design
ABC: an academic industrial-strength verification tool
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Incremental formal verification of hardware
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
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Constraints represent a key component of state-of-the-art verification tools based on compositional approaches and assume--guarantee reasoning. In recent years, most of the research efforts on verification constraints have focused on defining formats and techniques to encode, or to synthesize, constraints starting from the specification of the design. In this paper, we analyze the impact of constraints on the performance of model checking tools, and we discuss how to effectively exploit them. We also introduce an approach to explicitly derive verification constraints hidden in the design and/or in the property under verification. Such constraints may simply come from true design constraints, embedded within the properties, or may be generated in the general effort to reduce or partition the state space. Experimental results show that, in both cases, we can reap benefits for the overall verification process in several hard-to-solve designs, where we obtain speed-ups of more than one order of magnitude.