Embedding boolean expressions into logic programming
Journal of Symbolic Computation
Boolean unification - The story so far
Journal of Symbolic Computation
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Design Constraints in Symbolic Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Building Circuits from Relations
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Simplifying Boolean constraint solving for random simulation-vector generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Combinational equivalence checking through function transformation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Framework for Constrained Functional Verification
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Supporting sequential assumptions in hybrid verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Directed-simulation assisted formal verification of serial protocol and bridge
Proceedings of the 43rd annual Design Automation Conference
Hybrid Verification of Protocol Bridges
IEEE Design & Test
Optimal constraint-preserving netlist simplification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Interpolating functions from large Boolean relations
Proceedings of the 2009 International Conference on Computer-Aided Design
Speeding up model checking by exploiting explicit and hidden verification constraints
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic constraint generation for guided random simulation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Exploiting constraints in transformation-based verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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Modeling design environment with constraints instead of a traditional testbench is advantageous in a hybrid verification framework that encompasses simulation and formal verification. This movement is gaining popularity in industry and sparks research in the constraint-based environment modeling and stimulus generation problem. We present an approach, called constraint synthesis, to this problem. Constraint synthesis falls in the general category of parametric Boolean equation solving but is novel in utilizing don't care information unique to hardware constraints and heuristic variable removal to simplify the solution. Experimental results have demonstrated the effectiveness of the proposed approach.