Formal verification of an IBM CoreConnect processor local bus arbiter core
Proceedings of the 37th Annual Design Automation Conference
Constraint synthesis for environment modeling in functional verification
Proceedings of the 40th annual Design Automation Conference
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Combining Simulation and Guided Traversal for the Verification of Concurrent Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An effective guidance strategy for abstraction-guided simulation
Proceedings of the 44th annual Design Automation Conference
A Model Checking Approach to Protocol Conversion
Electronic Notes in Theoretical Computer Science (ENTCS)
SoC design approach using convertibility verification
EURASIP Journal on Embedded Systems - Model-driven high-level programming of embedded systems: selected papers from SLA++P'07 and SLA++P'08
Semiformal verification of temporal properties in automotive hardware dependent software
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic constraint generation for guided random simulation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Robust verification of protocol conversion and arbitration schemes of SoC bridges forms a significant component of the overall SoC verification. Formal verification provides a way to achieve this, but a naive approach often leads to explosion of the state space, and is impractical for most of today's protocols and bridges. This problem is further complicated in the presence of serial protocols, where control and data are mixed together and transactions continue for very great depths. White-box verification is not a feasible solution, since these bridges are often imported or generated from other sources, and internal information is not readily available. In this paper, we propose a black-box and hybrid approach to this problem, by judiciously mixing simulation and formal verification. We illustrate our approach by applying it to two dual stage bridges that perform serial to parallel protocol conversion and vice versa.