Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
A formal protocol conversion method
SIGCOMM '86 Proceedings of the ACM SIGCOMM conference on Communications architectures & protocols
Synthesis and verification of discrete controllers for robotics and manufacturing devices with temporal logic and the control-D system
Information and Computation - Special issue on FLOC '96
IEEE Transactions on Software Engineering
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Convertibility verification and converter synthesis: two faces of the same coin
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient On-the-Fly Model Checking for CTL
LICS '95 Proceedings of the 10th Annual IEEE Symposium on Logic in Computer Science
Bridge Over Troubled Wrappers: Automated Interface Synthesis
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Supervisory Control of Discrete Event Systems with CTL* Temporal Logic Specifications
SIAM Journal on Control and Optimization
Directed-simulation assisted formal verification of serial protocol and bridge
Proceedings of the 43rd annual Design Automation Conference
A Model Checking Approach to Protocol Conversion
Electronic Notes in Theoretical Computer Science (ENTCS)
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Compositional design of systems on chip from preverified components helps to achieve shorter design cycles and time to market. However, the design process is affected by the issue of protocol mismatches, where two components fail to communicate with each other due to protocol differences. Convertibility verification, which involves the automatic generation of a converter to facilitate communication between two mismatched components, is a collection of techniques to address protocol mismatches. We present an approach to convertibility verification using module checking. We use Kripke structures to represent protocols and the temporal logic ACTL to describe desired system behavior. A tableau-based converter generation algorithm is presented which is shown to be sound and complete. We have developed a prototype implementation of the proposed algorithm and have used it to verify that it can handle many classical protocol mismatch problems along with SoC problems. The initial idea for ACTL-based convertibility verification was presented at SLA++P '07 as presented in the work by Roopak Sinha et al. 2008.