Proceedings of the conference on Design, automation and test in Europe - Volume 1
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Automatic interface synthesis based on the classification of interface protocols of IPs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A formal approach to the protocol converter problem
Proceedings of the conference on Design, automation and test in Europe
Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SoC design approach using convertibility verification
EURASIP Journal on Embedded Systems - Model-driven high-level programming of embedded systems: selected papers from SLA++P'07 and SLA++P'08
An optimal power algorithm for interface design of System-on-Chip
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Formal model of a protocol converter
CATS '09 Proceedings of the Fifteenth Australasian Symposium on Computing: The Australasian Theory - Volume 94
Multi-clock SoC design using protocol conversion
Proceedings of the Conference on Design, Automation and Test in Europe
A formal approach to design space exploration of protocol converters
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic synthesis of interface circuits from simplified IP interface protocols
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
autoVHDL: a domain-specific modeling language for the auto-generation of VHDL core wrappers
Proceedings of the compilation of the co-located workshops on DSM'11, TMC'11, AGERE!'11, AOOPES'11, NEAT'11, & VMIL'11
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System-on-Chip (SoC) design methodologies rely heavilyon reuse of intellectual property (IP) blocks. IP reuse isa labour intensive and time consuming process as IP blocksoften have different communication interfaces. We presentan algorithm which automates the generation of provablycorrect HDL descriptions of interfaces between mismatchedIP communication protocols. We significantly improve andextend existing work by providing a solution which addressesdata mismatches, pipelining and differences in clockspeeds. These ideas have been implemented and the toolhas been used to synthesise wrappers and bridges for manySoC protocols.