Interfacing incompatible protocols using interface process generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Automatic synthesis of interfaces between incompatible protocols
DAC '98 Proceedings of the 35th annual Design Automation Conference
Automated composition of hardware components
DAC '98 Proceedings of the 35th annual Design Automation Conference
Synthesizing Converters Between Finite State Protocols
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Convertibility verification and converter synthesis: two faces of the same coin
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Bridge Over Troubled Wrappers: Automated Interface Synthesis
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
EWD: A metamodeling driven customizable multi-MoC system modeling framework
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Protocol Transducer Synthesis using Divide and Conquer approach
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
A formal approach to the protocol converter problem
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BALBOA: a component-based design environment for system models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System modeling and transformational design refinement in ForSyDe [formal system design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACS: automatic converter synthesis for SoC bus protocols
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
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Hardware module reuse is a standard solution to the problems of increasing complexity of chip architectures and pressure to reduce time to market. In the absence of a single module interface standard, predesigned modules for “plug-and-play” usually require a converter between incompatible interface protocols. Current approaches to automatic synthesis of protocol converters mostly lack formal foundations and either employ abstractions far removed from the HDL implementation level or grossly simplify the structure of the protocols considered. This work presents a state-machine-based formalism for modeling bus-based communication protocols and a notion of protocol compatibility and of correct conversion between incompatible protocols. This formalism is used to derive algorithms for checking protocol compatibility and for provably correct, automatic converter synthesis. Experiments with automatic converter synthesis between different configurations of widely used commercial bus protocols, such as AMBA AHB, ASB APB, and the Open Core Protocol (OCP) are discussed. The work here is unique in its combination of a completely formal approach and the use of a low abstraction level that enables precise modeling of protocol characteristics that is also close to HDL.