Sizing synchronization queues: a case study in higher level synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Hardware/software partitioning and minimizing memory interface traffic
EURO-DAC '94 Proceedings of the conference on European design automation
An approach to interface synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Interface co-synthesis techniques for embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Specification of interface components for synchronous data paths
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Grammar-based Hardware Synthesis of Data Communication Protocols
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Bus-Based Communication Synthesis on System-Level
ISSS '96 Proceedings of the 9th international symposium on System synthesis
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
MOCSYN: multiobjective core-based single-chip system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Exploiting intellectual properties in ASIP designs for embedded DSP software
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Validation in a component-based design flow for multicore SoCs
Proceedings of the 15th international symposium on System Synthesis
A protocol converter for nonblocking protocols
Integration, the VLSI Journal
Strategies for the integration of hardware and software IP components in embedded systems-on-chip
Integration, the VLSI Journal - Special issue: IP and design reuse
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A formal method for hardware IP design and integration under I/O and timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Hardware/software IP integration using the ROSES design environment
ACM Transactions on Embedded Computing Systems (TECS)
Efficient integration of pipelined IP blocks into automatically compiled datapaths
EURASIP Journal on Embedded Systems
A formal approach to the protocol converter problem
Proceedings of the conference on Design, automation and test in Europe
Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A formal approach to design space exploration of protocol converters
Proceedings of the Conference on Design, Automation and Test in Europe
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In order to automate design reuse, methods for composing system components must be developed. The goal of this research is to automate the process of generating interfaces between hardware subsystems. The algorithms presented here can be used to generate a cycle-accurate, synchronous interface between two hardware subsystems given an HDL model of each subsystem. These algorithms have been implemented in the POLARIS hardware composition tool and have been used to generate an interface between a MIPS microprocessor and the SRAM that comprises its secondary cache. Interface generation for the MIPS R4000 is described.