The Chinook hardware/software co-synthesis system
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Automated composition of hardware components
DAC '98 Proceedings of the 35th annual Design Automation Conference
HW/SW coverification performance estimation and benchmark for a 24 embedded RISC core design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Multilanguage design of heterogeneous systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Standards for system-level design: practical reality or solution in search of a question?
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Methodology for hardware/software co-verification in C/C++ (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Micronetwork-based integration for SOCs: 673
Proceedings of the 38th annual Design Automation Conference
Colif: A Design Representation for Application-Specific Multiprocessor SOCs
IEEE Design & Test
Designing and Programming the Emotion Engine
IEEE Micro
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design
Proceedings of the conference on Design, automation and test in Europe
Zipper VDSL: a solution for robust duplex communication over telephone lines
IEEE Communications Magazine
Multi-level software validation for NOC
Networks on chip
ESys.Net: a new solution for embedded systems modeling and simulation
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Automated Bus Generation for Multiprocessor SoC Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Strategies for the integration of hardware and software IP components in embedded systems-on-chip
Integration, the VLSI Journal - Special issue: IP and design reuse
A SystemC Refinement Methodology for Embedded Software
IEEE Design & Test
A formal method for hardware IP design and integration under I/O and timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
A new efficient EDA tool design methodology
ACM Transactions on Embedded Computing Systems (TECS)
Constrained algorithmic IP design for system-on-chip
Integration, the VLSI Journal
Generic discrete-continuous simulation model for accurate validation in heterogeneous systems design
Microelectronics Journal
A formalization of global simulation models for continuous/discrete systems
Proceedings of the 2007 Summer Computer Simulation Conference
Model Transformations for the Compilation of Multi-processor Systems-on-Chip
Generative and Transformational Techniques in Software Engineering II
A novel SoC platform based multi-IP verification and performance measurement
International Journal of Information and Communication Technology
A novel multi-IP verification methodology using an SoC platform
ACST '08 Proceedings of the Fourth IASTED International Conference on Advances in Computer Science and Technology
EUC'07 Proceedings of the 2007 conference on Emerging direction in embedded and ubiquitous computing
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Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable this integration, we use a design approach called component based-design approach. In this approach, the validation of system integration takes most of design efforts. This paper presents an automatic method of SoCs design validation. Based on a generic simulation wrapper architecture, the presented method provides automatic generation of executable models throughout different stages of SoC design flow. A case study of validating a VDSL application shows the effectiveness of the method.