Constrained algorithmic IP design for system-on-chip

Authors:
P. Coussy;E. Casseau;P. Bomel;A. Baganne;E. Martin
Affiliations:
LESTER Lab. FRE2734, UBS University, BP 92116, 56321 Lorient Cedex, France;LESTER Lab. FRE2734, UBS University, BP 92116, 56321 Lorient Cedex, France;LESTER Lab. FRE2734, UBS University, BP 92116, 56321 Lorient Cedex, France;LESTER Lab. FRE2734, UBS University, BP 92116, 56321 Lorient Cedex, France;LESTER Lab. FRE2734, UBS University, BP 92116, 56321 Lorient Cedex, France
Venue:
Integration, the VLSI Journal
Year:
2007

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Abstract

In the system on chip design context, RTL design of complex digital signal processing coprocessors can be improved by using algorithmic description as input for the synthesis process. System integration, that is a major step in SoC design, requires taking into account communication and timing constraints to design and integrate dedicated hardware accelerator. In this paper, we propose a design flow based on formal models that allows high-level synthesis under input/output timing constraints of DSP algorithms. Based on a generic architecture, the presented method provides automatic generation of customized hardware components. We show the effectiveness of our approach in a case study of a maximum a posteriori (MAP) algorithm for turbo decoding.