Memory accesses management during high level synthesis

Authors:
Gwenolé Corre;Eric Senn;Pierre Bomel;Nathalie Julien;Eric Martin
Affiliations:
University of South Brittany, LORIENT cedex, France;University of South Brittany, LORIENT cedex, France;University of South Brittany, LORIENT cedex, France;University of South Brittany, LORIENT cedex, France;University of South Brittany, LORIENT cedex, France
Venue:
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Year:
2004

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Abstract

We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final Compatibility Graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.