Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Validation in a component-based design flow for multicore SoCs
Proceedings of the 15th international symposium on System Synthesis
A Hardware-Software Codesign Methodology for DSP Applications
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Platform-Based Testbench Generation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design of Test Access Mechanism for AMBA-Based System-on-a-Chip
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
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It is well-known that in ASIC designs, verification is more difficult and time consuming than design itself. As the number of IPs in an SoC design increases, verifying multiple IPs together is really important to reduce time-to-market. In this paper, we propose a novel SoC platform based verification methodology which tests multiple IPs together using a single testbench. We've found that commercially available SoC platforms such as Altera Excalibur or Xilinx Virtex provide excellent environment in verifying the functionalities of mutually interactive multiple IPs with very low cost. In our methodology, embedded processor core built in the SoC device is used mainly for verification purposes, and it runs a C-based testbench. The mutually interactive IPs are programmed in the FPGA device. We implement a set of tools which consists of a communication interface and a wrapper generator. Using this platform, we have verified up to 5 IPs together successfully. Time and effort to verify complex IPs have been significantly reduced using this methodology.