Techniques and standards for image, video, and audio coding
Techniques and standards for image, video, and audio coding
Designing systems-on-chip using cores
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Validation in a component-based design flow for multicore SoCs
Proceedings of the 15th international symposium on System Synthesis
Bus-Based Communication Synthesis on System-Level
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
An architecture and compiler for scalable on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
Automated throughput-driven synthesis of bus-based communication architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
FABSYN: floorplan-aware bus architecture synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Model Based Synthesis of Embedded Software
SEUS '08 Proceedings of the 6th IFIP WG 10.2 international workshop on Software Technologies for Embedded and Ubiquitous Systems
Hardware-dependent software synthesis for many-core embedded systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
Proceedings of the 46th Annual Design Automation Conference
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The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor System-on-a-Chip (SoC). Our bus synthesis tool (BusSyn) uses this methodology to generate five different bus systems as examples: Bi-FIFO Bus Architecture (BFBA), Global Bus Architecture Version I (GBAVI), Global Bus Architecture Version III (GBAVIII), Hybrid bus architecture (Hybrid) and Split Bus Architecture (SplitBA). We verify and evaluate the performance of each bus system in the context of two applications: an Orthogonal Frequency Division Multiplexing (OFDM) wireless transmitter and an MPEG2 decoder. This methodology gives the designer a great benefit in fast design space exploration of bus architectures across a variety of performance impacting factors such as bus types, processor types and software programming style. In this paper, we show that BusSyn can generate buses that achieve superior performance when compared to a simple General Global Bus Architecture (GGBA) (e.g., 16.44% performance improvement in the case of OFDM transmitter) or when compared to the CoreConnect Bus Architecture (CCBA) (e.g., 15.54% peformance improvement in the case of MPEG2 decoder). In addition, the bus architecture generated by BusSyn is designed in a matter of seconds instead of weeks for the hand design of a custom bus system.