Simulated annealing for VLSI design
Simulated annealing for VLSI design
Stochastic evolution: a fast effective heuristic for some generic layout problems
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Genetic programming: on the programming of computers by means of natural selection
Genetic programming: on the programming of computers by means of natural selection
Formal verification of an IBM CoreConnect processor local bus arbiter core
Proceedings of the 37th Annual Design Automation Conference
LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
ARM System Architecture
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An Analysis of the Interacting Roles of Population Size and Crossover in Genetic Algorithms
PPSN I Proceedings of the 1st Workshop on Parallel Problem Solving from Nature
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic Model Refinement for Fast Architecture Exploration
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Automated Bus Generation for Multiprocessor SoC Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
System-level performance analysis for designing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
Automated throughput-driven synthesis of bus-based communication architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
FABSYN: floorplan-aware bus architecture synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
A priority assignment strategy of processing elements over an on-chip bus
Proceedings of the 2007 ACM symposium on Applied computing
Proceedings of the conference on Design, automation and test in Europe
Master Interface for On-chip Hardware Accelerator Burst Communications
Journal of VLSI Signal Processing Systems
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For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an SoC design. Furthermore, bus IP vendors provide software tools that automatically generate RTL codes of a bus once its designer configures it. Configurability, however, imposes more challenges upon designers because complexity involved in optimization increases exponentially as the number of parameters grows. In this paper, we present a novel approachwith which effort requirement can be dramatically reduced. An automated optimization tool we developed is used and it exploits a genetic algorithm for fast design exploration. This paper shows that the time for the optimizing task can be reduced by more than 90% when the tool is used and, more significantly the task can be done without an expert's hand while ending up with a better solution.