Protocol selection and interface generation for HW-SW codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
MOCSYN: multiobjective core-based single-chip system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 38th annual Design Automation Conference
Constraint-driven communication synthesis
Proceedings of the 39th annual Design Automation Conference
Latency-guided on-chip bus network design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
AMBA: Enabling Reusable On-Chip Designs
IEEE Micro
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Bus-Based Communication Synthesis on System-Level
ISSS '96 Proceedings of the 9th international symposium on System synthesis
SEAS: a system for early analysis of SoCs
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Automated Bus Generation for Multiprocessor SoC Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Fast Exploration of Bus-Based On-Chip Communication Architectures
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On wirelength estimations for row-based placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect performance estimation models for design planning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Proceedings of the conference on Design, automation and test in Europe
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Simultaneous on-chip bus synthesis and voltage scaling under random on-chip data traffic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Slack allocation based co-synthesis and optimization of bus and memory architectures for MPSoCs
Proceedings of the conference on Design, automation and test in Europe
SAMBA-bus: A high performance bus architecture for system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification
Journal of Signal Processing Systems
Electronic system-level synthesis methodologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip communication architecture exploration for processor-pool-based MPSoC
Proceedings of the Conference on Design, Automation and Test in Europe
Design of network-on-chip architectures with a genetic algorithm-based technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Systems Architecture: the EUROMICRO Journal
| Hi-index | 0.00 |
As system-on-chip (SoC) designs become more complex, it is becoming harder to design communication architectures to handle the ever increasing volumes of inter-component communication. Manual traversal of the vast communication design space to synthesize a communication architecture that meets performance requirements becomes infeasible. In this paper, we address this problem by proposing an automated approach for floorplan-aware bus architecture synthesis (FABSYN) to synthesize cost-effective, bus-based communication architectures that satisfy the performance constraints in a design. Our synthesis approach incorporates a high-level floorplanning and wire delay estimation engine to evaluate the feasibility of the synthesized bus architecture and detect bus cycle time violations early in the design flow, at the system level. We present case studies of network communication SoC subsystems for which we synthesized bus architectures, detected and eliminated timing violations, and generated core placements in a matter of hours instead of several days for a manual effort.