Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Bus-based communication synthesis on system level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 38th annual Design Automation Conference
Constraint-driven communication synthesis
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Utilization Bound for Aperiodic Tasks and Priority Driven Scheduling
IEEE Transactions on Computers
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint
Proceedings of the 43rd annual Design Automation Conference
FABSYN: floorplan-aware bus architecture synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simultaneous on-chip bus synthesis and voltage scaling under random on-chip data traffic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated bus generation for multiprocessor SoC design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architectures. In a real-time embedded system, task arrival rate, inter-task arrival time, and data size to be transferred are not uniform over time. This is due to the partial re-configuration of an embedded system to cope with dynamic workload. In this context, the traditional application specific bus architectures may fail to meet the real-time constraints. Thus, to incorporate the random behavior of on-chip communication, this work proposes an approach to synthesize an on-chip bus architecture, which is robust for a given distributions of random tasks. The randomness of communication tasks is characterized by three main parameters which are the average task arrival rate, the average inter-task arrival time, and the data size. For synthesis, an on-chip bus requirement is guided by the worst-case performance need, while the dynamic voltage scaling technique is used to save energy when the workload is low or timing slack is high. This, in turn, results in an effective utilization of communication resources under variable workload.