Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Bus-based communication synthesis on system level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Minimizing the required memory bandwidth in VLSI system realizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 38th annual Design Automation Conference
Constraint-driven communication synthesis
Proceedings of the 39th annual Design Automation Conference
Memory System Connectivity Exploration
Proceedings of the conference on Design, automation and test in Europe
A novel memory size model for variable-mapping in system level design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power analysis of system-level on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Efficient exploration of on-chip bus architectures and memory allocation
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint
Proceedings of the 43rd annual Design Automation Conference
FABSYN: floorplan-aware bus architecture synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Simultaneous on-chip bus synthesis and voltage scaling under random on-chip data traffic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated bus generation for multiprocessor SoC design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC
Proceedings of the 49th Annual Design Automation Conference
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In this paper, we present a bus and memory architectures co-synthesis technique. The co-synthesis problem is formulated as an optimization problem, where scheduling, allocation, and binding of tasks are done simultaneously in order to optimize the bus widths, the number of buses, and the memory sizes. As a main contribution, bus and memory architectures are optimized simultaneously by allocating different amount of slacks to them during co-synthesis. The method finds a balance of slack allocation for both bus and memory optimization. While the previous co-synthesis approaches do not consider the slack allocation technique, the synthesized bus and memory architectures will not be optimal in terms of area and energy consumption. The experimental results carried out on real-life applications show 19% and 24% reduction in bus and memory area, respectively and 37% reduction in energy overhead due to a bridge in compared to the previous co-synthesis approach.