Processor-memory coexploration using an architecture description language
ACM Transactions on Embedded Computing Systems (TECS)
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Slack allocation based co-synthesis and optimization of bus and memory architectures for MPSoCs
Proceedings of the conference on Design, automation and test in Europe
Processor Description Languages
Processor Description Languages
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In programmable embedded systems, the memory subsystemrepresents a major cost, performance and power bottle-neck.To optimize the system for such different goals, thedesigner would like to perform Design Space Exploration,evaluating different memory modules from a memory IP library,and selecting the most promising designs. However,while the memory modules are important, the rate at whichthe memory system can produce the data for the CPU is significantlyimpacted by the connectivity architecture betweenthe memory subsystem and the CPU. Thus, it is critical toconsider the connectivity architecture early in the design flow,in conjunction with the memory architecture. We present aconnectivity architecture exploration approach, evaluating awide range of cost, performance, and energy connectivity architectures.When coupled with our memory modules explo-rationapproach, we can significantly improve the system behavior.We present experiments on a set of large real-lifebenchmarks, showing significant performance improvementsfor varied cost and power characteristics, allowing the designerto tailor the performance, cost and power of the programmableembedded system.