Design of network-on-chip architectures with a genetic algorithm-based technique

Authors:
Glenn Leary;Krishnan Srinivasan;Krishna Mehta;Karam S. Chatha
Affiliations:
Department of Computer Science and Engineering, Arizona State University, Tempe, AZ;Sonics Inc., Milpitas, CA and Department of Computer Science and Engineering, Arizona State University, Tempe, AZ;Freescale Inc., Tempe, AZ and Department of Computer Science and Engineering, Arizona State University, Tempe, AZ;Department of Computer Science and Engineering, Arizona State University, Tempe, AZ
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

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Abstract

The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection architecture that can support the communication requirements for the SoC with the desired performance. This paper presents a genetic algorithm-based automated design technique that synthesizes an application specific NoC topology and routes the communication traces on the interconnection network. The technique operates on the system-level floorplan of the system on chip (SoC) and accounts for the power consumption in the physical links and the routers. The design technique solves a multi-objective problem of minimizing the power consumption and the router resources. It generates a Pareto curve of the solution set, such that each point in the curve represents a tradeoff between power consumption and associated number of NoC routers. The performance and quality of solutions produced by the technique are evaluated by experimentation with benchmark applications and comparisons with existing approaches.