Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Task generation and compile-time scheduling for mixed data-control embedded software
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Constraint-driven communication synthesis
Proceedings of the 39th annual Design Automation Conference
Embedded software generation from system level design languages
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Systemic Embedded Software Generation from SystemC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing Compiler
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
System-level power-performance trade-offs in bus matrix communication architecture synthesis
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Automotive Software Development for a Multi-Core System-on-a-Chip
SEAS '07 Proceedings of the 4th International Workshop on Software Engineering for Automotive Systems
Automatic generation of hardware dependent software for MPSoCs from abstract system specifications
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Automatic Layer-Based Generation of System-On-Chip Bus Communication Models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RTOS-aware refinement for TLM2.0-based HW/SW designs
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents synthesis of Hardware Dependent Software (HdS) for multicore and many-core designs using Embedded System Environment (ESE). ESE is a tool set, developed at UC Irvine, for transaction level design of multicore embedded systems. HdS synthesis is a key component of ESE backend design flow. We follow a design process that starts with an application model consisting of C processes communicating via abstract message passing channels. The application model is mapped to a platform net-list of SW and HW cores, buses and buffers. A high speed transaction level model (TLM) is generated to validate abstract communication between processes mapped to different cores. The TLM is further refined into a Pin-Cycle Accurate Model (PCAM) for board implementation. The PCAM includes C code for all the HdS layers including routing, packeting, synchronization and bus transfer. The generated HdS methods provide a library of application level services to the C processes on individual SW cores. Therefore, the application developer does not need to write low level HdS for board implementation. Synthesis results for an multi-core MP3 decoder design, using ESE, show that the HdS is generated in order of seconds, compared to hours of manual coding. The quality of synthesized code is comparable to manually written code in terms of performance and code size.