HW/SW coverification performance estimation and benchmark for a 24 embedded RISC core design

Authors:
Thomas W. Albrecht;Johann Notbauer;Stefan Rohringer
Affiliations:
Siemens, Austria, Erdberger Laende 26, A-1030 Vienna, Austria;Siemens, Austria, Erdberger Laende 26, A-1030 Vienna, Austria;Siemens, Austria, Erdberger Laende 26, A-1030 Vienna, Austria
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

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Abstract

This paper describes the benchmarking of a HW/SW-coverification design strategy. The benchmark results were the base for making a principal verification decision for an already ongoing project at Siemens AG, Public Communication Network Group. The intention for this benchmark was to verify whether commercial available coverification tools can handle the design complexity of an embedded system containing 24 embedded RISC cores and provides the necessary performance in terms of simulation speed and throughput.