Relative scheduling under timing constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-level synthesis from VHDL with exact timing constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
VHDL as Input for High-Level Synthesis
IEEE Design & Test
Procedure exlining: a new system-level specification transformation
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Procedure exlining: a transformation for improved system and behavioral synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Automated composition of hardware components
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Automatic generation of interprocess communication in the PARAGON system
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
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