DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
From Behavior to Structure: High-Level Synthesis
IEEE Design & Test
Compiling VHDL into a high-level synthesis design representation
EURO-DAC '92 Proceedings of the conference on European design automation
Flexible timing specification in a VHDL synthesis subset
EURO-DAC '92 Proceedings of the conference on European design automation
Semantics and synthesis of signals in behavioral VHDL
EURO-DAC '92 Proceedings of the conference on European design automation
Subtype concept of VHDL for synthesis constraints
EURO-DAC '92 Proceedings of the conference on European design automation
Synthesis of VHDL concurrent processes
EURO-DAC '94 Proceedings of the conference on European design automation
EURO-DAC '94 Proceedings of the conference on European design automation
Timing preserving interface transformations for the synthesis of behavioral VHDL
EURO-DAC '94 Proceedings of the conference on European design automation
Procedure exlining: a new system-level specification transformation
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Procedure exlining: a transformation for improved system and behavioral synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Analysis of different protocol description styles in VHDL for high-level synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Specification and management of timing constraints in behavioral VHDL
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Specification of interface components for synchronous data paths
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Specification, Planning, and Synthesis in a VHDL Design Environment
IEEE Design & Test
Scalable interprocedural register allocation for high level synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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High-level synthesis is defined, and the feasibility of high-level synthesis from a behavioral, sequential description in VHDL (VHSIC hardware description language) is examined. It is seen that in some cases the semantics and descriptive power of the language create difficulties for high-level synthesis, and in other cases the high-level synthesis framework used imposes limitations. Restrictions in the form of rules are suggested for overcoming these difficulties. It is shown that although VHDL semantics were initially defined in terms of simulation, they do not pose any fundamental problems for high-level synthesis.