Design representation and behavioral transformation for algorithmic level integrated circuit design
Design representation and behavioral transformation for algorithmic level integrated circuit design
VHDL synthesis using structured modeling
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Compiling VHDL into a high-level synthesis design representation
EURO-DAC '92 Proceedings of the conference on European design automation
Flexible timing specification in a VHDL synthesis subset
EURO-DAC '92 Proceedings of the conference on European design automation
Semantics and synthesis of signals in behavioral VHDL
EURO-DAC '92 Proceedings of the conference on European design automation
Subtype concept of VHDL for synthesis constraints
EURO-DAC '92 Proceedings of the conference on European design automation
Scheduling of behavioral VHDL by retiming techniques
EURO-DAC '94 Proceedings of the conference on European design automation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
VHDL as Input for High-Level Synthesis
IEEE Design & Test
Specification and management of timing constraints in behavioral VHDL
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Synchronous Controller Models for Synthesis from Communicating VHDL Processes
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
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