Knowledge based control in micro-architecture design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Chip-level modeling with VHDL
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The system architect's workbench
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
MILO: a microarchitecture and logic optimizer
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An Artificial Intelligence Approach to VLSI Design
An Artificial Intelligence Approach to VLSI Design
An intermediate representation for behavioral synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Compiling VHDL into a high-level synthesis design representation
EURO-DAC '92 Proceedings of the conference on European design automation
EURO-DAC '94 Proceedings of the conference on European design automation
IEEE Design & Test
Specification, Planning, and Synthesis in a VHDL Design Environment
IEEE Design & Test
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This paper describes the use of VHDL in a behavioral synthesis system. A structured modeling methodology is presented which suggests standard practices for writing VHDL descriptions which span a variety of design models. The VHDL Synthesis System (VSS) processes each of these input descriptions and produces a structural description of generic components.