High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Experiences in functional validation of a high level synthesis system
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis of VHDL concurrent processes
EURO-DAC '94 Proceedings of the conference on European design automation
EURO-DAC '94 Proceedings of the conference on European design automation
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
High-Level VLSI Synthesis
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
DSS: A Distributed High-Level Synthesis System
IEEE Design & Test
Hierarchical behavioral partitioning for multicomponent synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
Formal Methods in System Design
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VHDL permits design descriptions with communicating multiple processes and provides signal assignments and wait statements to facilitate coordination and communication among the processes These constructs lead to concise behavioral specifications but make controller generation in high level synthesis difficult. Current work on synthesis from VHDL restricts the behavioral subset, excluding or limiting the use of some of these constructs, thus leading to simple controller structures. Our paper proposes a controller model based on multiple, synchronous, communicating finite state machines. The proposed controller model permits the use of multiple processes with signal assignments and wait statements in behavioral specifications.