Combining verification and simulation
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Distributed design-space exploration for high-level synthesis systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Formal Verification of Hardware Design
Formal Verification of Hardware Design
VHDL, Hardware Description and Design
VHDL, Hardware Description and Design
Computer Structures: Principles and Examples
Computer Structures: Principles and Examples
Simulation-Based Verification for High-Level Synthesis
IEEE Design & Test
DSS: A Distributed High-Level Synthesis System
IEEE Design & Test
Functional testing of digital systems
DAC '83 Proceedings of the 20th Design Automation Conference
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
Formal Methods in System Design
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Synchronous Controller Models for Synthesis from Communicating VHDL Processes
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
High level testbench generation for VHDL models
ECBS'99 Proceedings of the 1999 IEEE conference on Engineering of computer-based systems
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