Compiling VHDL into a high-level synthesis design representation
EURO-DAC '92 Proceedings of the conference on European design automation
Semantics and synthesis of signals in behavioral VHDL
EURO-DAC '92 Proceedings of the conference on European design automation
VHDL as Input for High-Level Synthesis
IEEE Design & Test
DSS: A Distributed High-Level Synthesis System
IEEE Design & Test
Specification, Planning, and Synthesis in a VHDL Design Environment
IEEE Design & Test
Timing constraint specification and synthesis in behavioral VHDL
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Multiple-process behavioral synthesis for mixed hardware-software systems
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Hardware/software partitioning of VHDL system specifications
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Synchronous parallel controller synthesis from behavioural multiple-process VHDL description
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Specification and management of timing constraints in behavioral VHDL
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Modeling of mixed control and dataflow system in MASCOT
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware/Software Embedded System Specifiaction and Design Using Ada and VHDL
Ada-Europe '99 Proceedings of the 1999 Ada-Europe International Conference on Reliable Software Technologies
Synchronous Controller Models for Synthesis from Communicating VHDL Processes
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Behavioral Synthesis of Complex Parallel Controllers
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
High-level Synthesis of Multi-process Behavioral Descriptions
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Hardware/Software Partitioning with Iterative Improvement Heuristics
ISSS '96 Proceedings of the 9th international symposium on System synthesis
VHDL system-level specification and partitioning in a hardware/software co-synthesis environment
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
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