Synchronous parallel controller synthesis from behavioural multiple-process VHDL description

Authors:
K. Bilinski;E. Dagless;J. Mirkowski
Affiliations:
Dept. of Electrical & Electronic Eng., University of Bristol, Bristol BS8 1TR, United Kingdom;Dept. of Electrical & Electronic Eng., University of Bristol, Bristol BS8 1TR, United Kingdom;Dept. of Computer Engineering & Electronics, Higher College of Engineering, 65-246 Zielona Gora, Poland
Venue:
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Year:
1996

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