Process graph analyzer: a front end tool for VHDL behavior synthesis
Proceedings of the Twenty-First Annual Hawaii International Conference on Architecture Track
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
A VHDL primer
Synthesis of VHDL concurrent processes
EURO-DAC '94 Proceedings of the conference on European design automation
Multiple-process behavioral synthesis for mixed hardware-software systems
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Performance analysis of a system of communicating processes
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Synchronization detection for multi-process hierarchical synthesis
Proceedings of the 11th international symposium on System synthesis
Communicating sequential processes
Communications of the ACM
IEEE Std 802.3b, C, D, and E - 1989: Supplements to Carrier Sense Multiple Access with Collision Detection (Csma-CD) Access Method and Physical Layer Specifications
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
High-Level VLSI Synthesis
Worst-case performance analysis of parallel, communicating software processes
Proceedings of the tenth international symposium on Hardware/software codesign
Synchronization of communicating modules and processes in high level synthesis
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Exploiting Program Branch Probabilities in Hardware Compilation
IEEE Transactions on Computers
Modeling and simulation in a formal design framework
Proceedings of the 6th Balkan Conference in Informatics
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This paper presents a new high-level synthesis methodology togenerate optimized implementations for multi-process behavioraldescriptions. The concurrent communicating processes specificationparadigm is widely used in digital circuit and system design,and is employed in all popular hardware description languages.It has been shown that interprocess communication andsynchronization can result in complex timing inter-dependencies,which significantly affect the performance of a multi-process system.However, previous research on high-level synthesis typicallytakes a one-process-at-a-time approach, and the effects of inter-processcommunication and synchronization are ignored whenperforming tasks such as scheduling, resource sharing, etc.In this paper, we demonstrate that state-of-the-art high-levelsynthesis tools can generate significantly sub-optimal implementationsfor behaviors that contain concurrent communicating processes.We present an analysis of how inter-process communicationimpacts high-level synthesis steps, and describe a newmethodology to adapt existing high-level synthesis tools to optimizemulti-process descriptions. Our methodology is basedon executing multi-process performance analysis and process-by-processscheduling in an iterative manner. The results of performanceanalysis are used to identify critical and near-critical operations,and to judiciously partition the global resource budgetinto constraints for each process. The process-level constraintsare used to drive scheduling for individual processes, so as tospeed up the overall system critical path. We present algorithmsfor key steps in the proposed methodology.We have performed extensive experiments in the context of acommercial high-level design flow to evaluate the proposed techniques.The results clearly demonstrate the utility of our techniquesin synthesizing implementations with superior area, performance,and energy consumption. For example, up to 40.0%performance improvement (average of 35.6%) was achieved withlittle or no area overheads (average of 4.8%). In effect, the proposedtechniques lead to a shift of the entire area-delay trade-offcurve for a design to include superior designs that were hithertoinfeasible. Our techniques also simultaneously result in upto 50.0% (average of 33.5%) improvement in energy and up to69.0% (average of 58.3%) in the energy-delay product.