Specification and management of timing constraints in behavioral VHDL

Relative scheduling under timing constraints

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference

Synthesis of VHDL concurrent processes

EURO-DAC '94 Proceedings of the conference on European design automation

Scheduling of behavioral VHDL by retiming techniques

EURO-DAC '94 Proceedings of the conference on European design automation

A transformation for integrating VHDL behavioral specification with synthesis and software generation

EURO-DAC '94 Proceedings of the conference on European design automation

Timing constraint specification and synthesis in behavioral VHDL

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation

VHDL as Input for High-Level Synthesis

IEEE Design & Test