Flexible timing specification in a VHDL synthesis subset

The IBM VHDL design system

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference

Relative scheduling under timing constraints

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference

Abstract data types and high-level synthesis

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference

High-level synthesis from VHDL with exact timing constraints

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

HERCULES—a system for high-level synthesis

DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference

Communicating sequential processes

Communications of the ACM

The Synthesis Approach to Digital System Design

The Synthesis Approach to Digital System Design

VHDL as Input for High-Level Synthesis

IEEE Design & Test