Automatic production of controller specifications from control and timing behavioral descriptions
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Relative scheduling under timing constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Global hardware synthesis from behavioral dataflow descriptions
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
DAC '80 Proceedings of the 17th Design Automation Conference
Flexible timing specification in a VHDL synthesis subset
EURO-DAC '92 Proceedings of the conference on European design automation
Scheduling of behavioral VHDL by retiming techniques
EURO-DAC '94 Proceedings of the conference on European design automation
Timing preserving interface transformations for the synthesis of behavioral VHDL
EURO-DAC '94 Proceedings of the conference on European design automation
Behavioral synthesis methodology for HDL-based specification and validation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Storage optimization by replacing some flip-flops with latches
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Specification of interface components for synchronous data paths
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Verification by simulation comparison using interface synthesi
Proceedings of the conference on Design, automation and test in Europe
An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions
ISSS '96 Proceedings of the 9th international symposium on System synthesis
A formal method for hardware IP design and integration under I/O and timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
Performance-driven synthesis in controller-datapath systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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