High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
The Princeton University behavioral synthesis system
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
High-level synthesis from VHDL with exact timing constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Edge-triggering vs. two-phase level-clocking
Proceedings of the 1993 symposium on Research on integrated systems
A designer's guide to VHDL synthesis
A designer's guide to VHDL synthesis
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Tolerating process variations in high-level synthesis using transparent latches
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
HLS-l: a high-level synthesis framework for latch-based architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
HLS-l: high-level synthesis of high performance latch-based circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the great lakes symposium on VLSI
A statistical approach to the timing-yield optimization of pipeline circuits
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
| Hi-index | 0.00 |