REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Storage optimization by replacing some flip-flops with latches
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Low power, testable dual edge triggered flip-flops
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
New methods to color the vertices of a graph
Communications of the ACM
Low-power high-level synthesis using latches
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Digital System Clocking: High-Performance and Low-Power Aspects
Digital System Clocking: High-Performance and Low-Power Aspects
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Optimal Clock Period for Synthesized Data Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Performance optimization using template mapping for datapath-intensive high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-driven high-level synthesis with bit-level chaining and clock selection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
HLS-l: a high-level synthesis framework for latch-based architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rather than from behavioral description, which can be synthesized to RTL via high-level synthesis (HLS). Sequencing overhead is one of the factors for this performance gap; the choice between latch and flip-flop is not typically taken into account during HLS, even though it affects all the steps of HLS. HLS-l is a new design framework that employs high-performance latches during scheduling, allocation, and controller synthesis. Its main feature is a new scheduler that is based on a concept of phase step (as opposed to conventional control step), which allows us scheduling in finer granularity, register allocation that resolves the conflict of latch being read and written at the same time, and controller synthesis that exploits dual-edge triggered storage elements to support phase step based scheduling. In experiments on benchmark designs implemented in 1.2 V, 65-nm CMOS technology, HLS-l reduced latency by 16.6% on average, with 9.5% less circuit area, compared to the designs produced by conventional HLS.