A multiple clocking scheme for low-power RTL design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
REWIRED: REgister Write Inhibition by REsource Dedication
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Tolerating process variations in high-level synthesis using transparent latches
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
HLS-l: a high-level synthesis framework for latch-based architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
HLS-l: high-level synthesis of high performance latch-based circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the great lakes symposium on VLSI
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High-level synthesis using latches has many merits in power, area and even in speed. But latches cannot be read and written at the same time and usually requires two-phase non-overlapping clock that is unpleasant choice for short-term design. In this paper we propose a storage allocation method that makes it possible to use latches as storage elements in single clocking scheme. The proposed method modifies the lifetime of variables slightly so that it can be applied to any high-level synthesis systems with small modification. The experimental results show 39 ~ 65% reduction in power consumption within almost same area compared to the conventional power management scheme using clock gating.