REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Storage optimization by replacing some flip-flops with latches
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Low-power high-level synthesis using latches
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Tolerating process variations in high-level synthesis using transparent latches
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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Flip-flop (FF)/latch-based design has advantages on such as area and power compared to single register-type design (only FFs or latches). Considering FF/latch-based design at high-level synthesis is necessary, because resource binding process significantly affects the quality of resulting circuits. A major downside of FF/latch-based design is the increase in resources (functional units and registers) due to the modification of the lifetimes of operations and data. Therefore, as a first step, this paper addresses the datapath design problem in which resource binding and register-type selection are simultaneously optimized for resource optimization. An efficient comprehensive framework is presented, which has flexibility to incorporate other design objectives. Experiments show that the proposed approach can generate resource-efficient FF/latch-based datapaths.