Synthesis-for-testability of controller-datapath pairs that use gated clocks
Proceedings of the 37th Annual Design Automation Conference
Low-power high-level synthesis using latches
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register Transformations with Multiple Clock Domains
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
ILP models for simultaneous energy and transient power minimization during behavioral synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multivoltage multifrequency low-energy synthesis for functionally pipelined datapath
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A power-efficient processor core for reactive embedded applications
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
| Hi-index | 0.00 |
This paper presents a resource allocation technique to design low-power register-transfer-level datapaths. The basis of this technique is to use a multiple clocking scheme of n nonoverlapping clocks, by dividing the frequency f of a single clock into n cycles, to partition the circuit into n disjoint modules and assign each module to a distinct clock, and to operate each module only during its corresponding duty cycle, thus clocking each module by a frequency f/n to reduce power. However, the overall effective frequency of the circuit remains f, i.e., the single clock frequency. Further power reduction is also obtained by tradeoffs between voltage, power, and delay across multiple clock partitions. Power savings up to 50% of the proposed multiple clocking scheme in comparison to single gated clock designs are also reported.