Digital processing of signals (2nd ed)
Digital processing of signals (2nd ed)
Optimal VLSI architectural synthesis: area, performance and testability
Optimal VLSI architectural synthesis: area, performance and testability
Module assignment for low power
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Power management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multiple clocking scheme for low-power RTL design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power memory mapping through reducing address bus activity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Algorithms for VLSI Design Automation
Algorithms for VLSI Design Automation
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
High-level synthesis for low power based on network flow method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
High-level macro-modeling and estimation techniques for switching activity and power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A framework for energy and transient power reduction during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A game theoretic approach for power optimization during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Signal Processing
SCALP: an iterative-improvement-based low-power data path synthesis system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-reliability, low-energy microarchitecture synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Register binding-based RTL power management for control-flow intensive designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect-aware low-power high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multivoltage multifrequency low-energy synthesis for functionally pipelined datapath
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using speculative functional units in high level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
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Research work done has shown that power consumption in digital integrated circuits can be effectively reduced by reducing the switching activity occurring on the functional modules. High-level synthesis of digital integrated circuits for low power often optimizes the switching activity during the two main synthesis processes, operation scheduling and module binding, which are usually performed one control step at a time in two separated stages. As the two processes are strongly interdependent, separate optimization of switching activity in a step-by-step manner frequently leads to sub-optimal solutions. In this paper, we propose a novel look-ahead synthesis technique with backtracking for the reduction of switching activity in low power high-level synthesis, which not only performs the scheduling and binding simultaneously in an integrated manner using a weighted bipartite technique, but also employs a branch and bound approach with look-ahead evaluation of switching activity for one or more control steps. The look-ahead technique generates multiple schedulings and bindings at the same time in one control step and uses each of them to generate more schedulings and bindings for the next one or more control steps. The best scheduling and binding pattern is then used for backtracking, therefore, effectively reducing the probability for the solutions to fall into local minimum. We tested the look-ahead algorithm with several published benchmarks and the experimental results obtained show that the switching activity can be reduced significantly, with an average of more than 50% reduction in switching activity for the tested benchmarks.