ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis

Authors:
Saraju P. Mohanty;N. Ranganathan;Sunil K. Chappidi
Affiliations:
-;-;-
Venue:
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Year:
2004

Citing 0
Cited 6

Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints

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A look-ahead synthesis technique with backtracking for switching activity reduction in low power high-level synthesis

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Simultaneous operation scheduling and operation delay selection to minimize cycle-by-cycle power differential

EUC'07 Proceedings of the 2007 conference on Emerging direction in embedded and ubiquitous computing
Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simultaneous scheduling, allocation, binding, re-ordering, and encoding for crosstalk pattern minimization during high-level synthesis

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Variability-aware architecture level optimization techniques for robust nanoscale chip design

Computers and Electrical Engineering

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Abstract

The reduction of peak power, peak power differential,average power and energy are equally important in thedesign of low-power battery driven portable applications.In this paper, we introduce a parameter called "cyclepower function" (CPF-DFC) that captures the above powercharacteristics in the context of multiple supply voltage(MV) and dynamic frequency clocking (DFC) based designs.Further, we present ILP formulations for the minimizationof CPF-DFC during datapath scheduling. We conductedexperiments on selected high-level synthesis benchmarksfor various resource constraints. Experimental results showthat significant reduction in power, energy, and energy delayproduct, can be obtained using the proposed method.