System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Early evaluation techniques for low power binding
Proceedings of the 2002 international symposium on Low power electronics and design
Bus optimization for low-power data path synthesis based on network flow method
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An integrated data path optimization for low power based on network flow method
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Coupling-aware high-level interconnect synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
High-level synthesis for low power based on network flow method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Electromigration-aware dynamic routing algorithm for network-on-chip applications
International Journal of High Performance Systems Architecture
Dynamic memory access management for high-performance DSP applications using high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Continuous scaling of device dimensions has accelerated the power dissipation and electromigration-induced reliability degradation in integrated circuits. Submicrometer scaling increases the fraction of on-chip energy dissipated on long interconnects and buses. In addition, submicrometer-level scaling increases current density in long interconnects and buses, causing structural damage in metal lines due to electromigration (a major failure phenomenon in integrated circuits). We present algorithms for synthesizing high-reliability, low-energy microarchitectures. This can be realized by judiciously binding and scheduling the data transfers of a control-data-flow graph representation of an application onto the buses in the microarchitecture. The algorithm considers (i) correlations between data transfers, (ii) constraints on the number of buses, and (iii) area and delay