Optimal scheduling and allocation of embedded VLSI chips
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
System clock estimation based on clock slack minimization
EURO-DAC '92 Proceedings of the conference on European design automation
Timing estimation for behavioral descriptions
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
An Efficient Technique for Mapping RTL Structures onto FPGAs
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
A Heuristic for Clock Selection in High-Level Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
HLS-l: a high-level synthesis framework for latch-based architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
HLS-l: high-level synthesis of high performance latch-based circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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For technologies with significant interconnection delays, optimal clock period selection before/during high-level synthesis is not practical. In our approach, we start with a synthesized RTL data path structure, perform place and route and back-annotate the interconnection delays. A set of potentially optimal clock periods are chosen by evaluating 'critical' paths to minimize the dead time associated with operations. Finally, the controller costs at these clock periods along with the execution times decide the optimal clock period. Extensive experimental results on data paths synthesized from high-level synthesis benchmarks establish both the utility as well as the efficiency of our approach.