A statistical approach to the timing-yield optimization of pipeline circuits

Authors:
Chin-Hsiung Hsu;Szu-Jui Chou;Jie-Hong R. Jiang;Yao-Wen Chang
Affiliations:
Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan;Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan;Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan;Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan
Venue:
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Year:
2007

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Abstract

The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern circuit designs may suffer from design uncertainties, unpredictable in the design phase or even after manufacturing. This paper presents an optimization technique to make pipeline circuits robust against delay variations and thus maximize timing yield. By trading larger flip-flops for smaller latches, the proposed approach can be used as a post-synthesis or post-layout optimization tool, allowing accurate timing information to be available. Experimental results show an average of 31% timing yield improvement for pipeline circuits. They suggest that our method is promising for high-speed designs and is capable of tolerating clock variations.