An efficient design-for-verification technique for HDLs
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A Design-for-Verification Technique for Functional Pattern Reduction
IEEE Design & Test
Hybrid Approach to Faster Functional Verification with Full Visibility
IEEE Design & Test
Planar Feedback Vertex Set and Face Cover: Combinatorial Bounds and Subexponential Algorithms
Graph-Theoretic Concepts in Computer Science
A statistical approach to the timing-yield optimization of pipeline circuits
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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Finding the minimum feedback vertex set (MFVS) in a graph is an important problem for a variety of computer-aided design (CAD) applications and graph reduction plays an important role in solving this intractable problem. This paper is largely concerned with three new and powerful reduction operations. Each of these operations defines a new class of graphs, strictly larger than the class of contractible graphs [Levy and Low (1988)] in which the MFVS can be found in polynomial-time complexity. Based on these operations, an exact algorithm run on branch and bound manner is developed. This exact algorithm uses a good heuristic to find out an initial solution and a good bounding strategy to prune the solution space. To demonstrate the efficiency of our algorithms, we have implemented our algorithms and applied them to solving the partial scan problem in ISCAS'89 benchmarks. The experimental results show that if our three new contraction operations are applied, 27 out of 31 circuits in ISCAS'89 benchmarks can be fully reduced. Otherwise, only 12 out of 31 can be fully reduced. Furthermore, for all ISCAS'89 benchmarks our exact algorithm can find the exact cutsets in less than 3 s (CPU time) on a SUN-UltraII workstation. Therefore, the new contraction operations and our algorithms are demonstrated to be very effective in the partial scan application