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Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Proceedings of the 41st annual Design Automation Conference
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Proceedings of the 41st annual Design Automation Conference
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Proceedings of the 41st annual Design Automation Conference
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Proceedings of the 41st annual Design Automation Conference
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Proceedings of the 41st annual Design Automation Conference
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Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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ICCD '04 Proceedings of the IEEE International Conference on Computer Design
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Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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Proceedings of the 42nd annual Design Automation Conference
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
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Proceedings of the 43rd annual Design Automation Conference
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Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
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Proceedings of the 44th annual Design Automation Conference
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Proceedings of the 44th annual Design Automation Conference
Clustering based pruning for statistical criticality computation under process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Timing budgeting under arbitrary process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 45th annual Design Automation Conference
Incremental criticality and yield gradients
Proceedings of the conference on Design, automation and test in Europe
Variability driven gate sizing for binning yield optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
Statistical ordering of correlated timing quantities and its application for path ranking
Proceedings of the 46th Annual Design Automation Conference
Fast and accurate statistical criticality computation under process variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA design for timing yield under process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Post-manufacture tuning for nano-CMOS yield recovery using reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 47th Design Automation Conference
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Proceedings of the Conference on Design, Automation and Test in Europe
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With the increased significance of leakage power and performance variability, the yield of a design is becoming constrained both by power and performance limits, thereby significantly complicating circuit optimization. In this paper, we propose a new optimization method for yield optimization under simultaneous leakage power and performance limits. The optimization approach uses a novel leakage power and performance analysis that is statistical in nature and considers the correlation between leakage power and performance to enable accurate computation of circuit yield under power and delay limits. We then propose a new heuristic approach to incrementally compute the gradient of yield with respect to gate sizes in the circuit with high efficiency and accuracy. We then show how this gradient information can be effectively used by a non-linear optimizer to perform yield optimization. We consider both inter-die and intra-die variations with correlated and random components. The proposed approach is implemented and tested and we demonstrate up to 40% yield improvement compared to a deterministically optimized circuit.