Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
Circuit optimization using statistical static timing analysis
Proceedings of the 42nd annual Design Automation Conference
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing using incremental parameterized statistical timing analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On the futility of statistical power optimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On confidence in characterization and application of variation models
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Evaluating statistical power optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post sign-off leakage power optimization
Proceedings of the 48th Design Automation Conference
Clustering-based simultaneous task and voltage scheduling for NoC systems
Proceedings of the International Conference on Computer-Aided Design
Timing yield optimization via discrete gate sizing using globally-informed delay PDFs
Proceedings of the International Conference on Computer-Aided Design
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Leakage power is becoming an increasingly important component of total chip power consumption for nanometer IC designs. Minimization of leakage power unavoidably enforces the consideration of the key sources of process variations, namely transistor channel length and threshold variations, since both have a significant impact on timing and leakage power. However, the statistical nature of chip performances often requires the use of expensive statistical analysis and optimization techniques in a leakage minimization task, contributing to high computational complexity. Further, the commonly used discrete cell libraries bring specific difficulty for design optimization and render pure continuous sizing and VT optimization algorithm suboptimal. In this paper, we present a fast yet effective approach to statistical leakage power reduction via gate sizing and multiple VT assignment. The proposed technique achieves the runtime efficiency via the use of the novel concept of equi-slack shells and performs fast leakage power reduction on the basis of shells while maintaining the timing yield. When combined with a finer grained gate-based post tuning step, the presented technique achieves Superior runtime efficiency while offering significant leakage power reduction.