Energy minimization using multiple supply voltages
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Clustering Algorithms
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
A Low-Latency FIFO for Mixed-Clock Systems
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Voltage-frequency island partitioning for GALS-based networks-on-chip
Proceedings of the 44th annual Design Automation Conference
Statistical leakage power minimization using fast equi-slack shell based optimization
Proceedings of the 44th annual Design Automation Conference
Application-driven floorplan-aware voltage island design
Proceedings of the 45th annual Design Automation Conference
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
Proceedings of the 45th annual Design Automation Conference
Network flow-based power optimization under timing constraints in MSV-driven floorplanning
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A voltage-frequency island aware energy optimization framework for networks-on-chip
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Multi-voltage floorplan design with optimal voltage assignment
Proceedings of the 2009 international symposium on Physical design
Proceedings of the 47th Design Automation Conference
Design time body bias selection for parametric yield improvement
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient design space exploration for component-based system design
Proceedings of the International Conference on Computer-Aided Design
Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications
Proceedings of the Conference on Design, Automation and Test in Europe
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Networks-on-chip (NoC) is emerging as a promising communication structure, which is scalable with respect to chip complexity. Meanwhile, latest chip designs are increasingly leveraging multiple voltage-frequency domains for energy-efficiency improvement. In this work, we propose a simultaneous task and voltage scheduling algorithm for energy minimization in NoC based designs. The energy-latency tradeoff is handled by Lagrangian relaxation. The core algorithm is a clustering based approach which not only assigns voltage levels and starting time to each task (or Processing Element) but also naturally finds voltage-frequency clusters. Compared to a recent previous work, which performs task scheduling and voltage assignment sequentially, our method leads to an average of 20% energy reduction.