An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
Towards formal probabilistic power-performance design space exploration
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Application of fast SOCP based statistical sizing in the microprocessor design flow
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Statistical technology mapping for parametric yield
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing using incremental parameterized statistical timing analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical circuit optimization considering device andinterconnect process variations
Proceedings of the 2007 international workshop on System level interconnect prediction
An efficient algorithm for statistical circuit optimization using Lagrangian relaxation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Timing budgeting under arbitrary process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Soft-edge flip-flops for improved timing yield: design and optimization
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Robust gate sizing via mean excess delay minimization
Proceedings of the 2008 international symposium on Physical design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A linear programming formulation for security-aware gate sizing
Proceedings of the 18th ACM Great Lakes symposium on VLSI
An expected-utility based approach to variation aware VLSI optimization under scarce information
Proceedings of the 13th international symposium on Low power electronics and design
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
On the futility of statistical power optimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A fuzzy optimization approach for variation aware power minimization during gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware multimetric optimization during gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing-based placement considering uncertainty due to process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluating statistical power optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
Gene modification identification under flux capacity uncertainty
Proceedings of the 50th Annual Design Automation Conference
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In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nanometer regime. We present a statistical sizing approach that takes into account randomness in gate delays by formulating a robust linear program that can be solved efficiently. We demonstrate the efficiency and computational tractability of the proposed algorithm on the various ISCAS'85 benchmark circuits. Across the benchmarks, compared to the deterministic approach, the power savings range from 23-30% for the same timing target and the yield level, the average power saving being 28%.The runtime is reasonable, ranging from a few seconds to around 10 mins, and grows linearly.