Towards formal probabilistic power-performance design space exploration

Authors:
Joonsoo Kim;Michael Orshansky
Affiliations:
The University of Texas at Austin;The University of Texas at Austin
Venue:
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Year:
2006

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Abstract

We describe a formal probabilistic power-performance design space exploration technique. The technique aims at enabling hierarchical design space exploration based on a fully probabilistic description of power-performance tradeoffs. Probabilistic Pareto sets in power-performance space are proposed as canonical encodings of the power and delay tradeoffs in designs under any source of uncertainty. An algorithm to compute a composite probabilistic power-performance Pareto set for series or parallel connections of circuit blocks is also developed and validated. The algorithm is based on numerical convolution and is suitable for micro-architecture pipeline design exploration in the presence of process variability.