First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A New Statistical Optimization Algorithm for Gate Sizing
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
Interval-valued statistical modeling of oxide chemical-mechanical polishing
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficient algorithms for buffer insertion in general circuits based on network flow
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing using incremental parameterized statistical timing analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical gate sizing for timing yield optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Variability driven gate sizing for binning yield optimization
Proceedings of the 43rd annual Design Automation Conference
Robust estimation of parametric yield under limited descriptions of uncertainty
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fast min-cost buffer insertion under process variations
Proceedings of the 44th annual Design Automation Conference
Fast and exact transistor sizing based on iterative relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Unified Theory of Timing Budget Management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Timing budgeting under process variations is an important step in a statistical optimization flow. We propose a novel formulation of the problem where budgets are statistical instead of deterministic as in existing works. This new formulation considers the changes of both the means and variances of delays, and thus can reduce the timing violation introduced by ignoring the changes of variances. We transform the problem to a linear programming problem using a robust optimization technique. Our approach can be used in late-stage design where the detailed distribution information is known, and is most useful in early-stage design since our approach does not assume specific underlying distributions. In addition, with the help of block-level timing budgeting, our approach can reduce the timing pessimism. Our approach is applied to the leakage power minimization problem. The results demonstrate that our approach can reduce timing violation from 690ps to Ops, and the worst total leakage power by 17.50% on average.