Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Polynomial Methods for Separable Convex Optimization in Unimodular Linear Spaces with Applications
SIAM Journal on Computing
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Delay bounded buffered tree construction for timing driven floorplanning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Simultaneous routing and buffer insertion with restrictions on buffer locations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Meeting delay constraints in DSM by minimal repeater insertion
DATE '00 Proceedings of the conference on Design, automation and test in Europe
The scaling challenge: can correct-by-construction design help?
Proceedings of the 2003 international symposium on Physical design
An O(nlogn) time algorithm for optimal buffer insertion
Proceedings of the 40th annual Design Automation Conference
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Solving the Convex Cost Integer Dual Network Flow Problem
Management Science
A fast algorithm for identifying good buffer insertion candidate locations
Proceedings of the 2004 international symposium on Physical design
A Probabilistic Approach to Buffer Insertion
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Flexible Data Structure for Efficient Buffer Insertion
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Accurate estimation of global buffer delay within a floorplan
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Buffer insertion in large circuits with constructive solution search techniques
Proceedings of the 43rd annual Design Automation Conference
Fast min-cost buffer insertion under process variations
Proceedings of the 44th annual Design Automation Conference
Timing budgeting under arbitrary process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Circuit-wise buffer insertion and gate sizing algorithm with scalability
Proceedings of the 45th annual Design Automation Conference
A power-efficient multipin ILP-based routing technique
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Network flow-based simultaneous retiming and slack budgeting for low power design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Low power discrete voltage assignment under clock skew scheduling
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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With shrinking VLSI feature sizes and increasing overall chip areas, buffering has emerged as an effective solution to the problem of growing interconnect delays in modern designs. The problem of buffer insertion in a single net has been the focus of most previous researches. However, efficient algorithms for buffer insertion in whole circuits are generally needed. In this paper, we relate the timing constrained minimal buffer insertion problem to the min-cost flow dual problem, and propose two algorithms based on min-cost flow and min-cut techniques, respectively, to solve it in combinational circuits. We compare our approaches to a traditional approach based on Lagrangian relaxation. Experimental results demonstrate that our approaches are efficient and effective. On the average, our approaches achieve 45% and 39% reduction, respectively, on the number of buffers inserted in comparison to the traditional approach.